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19-1309; Rev 0; 10/97
5-Tap Silicon Delay Line
_______________General Description
The MXD1005 silicon delay line offers five equally spaced taps with delays ranging from 12ns to 250ns and a nominal accuracy of 2ns or 3%, whichever is greater. Relative to hybrid solutions, this device offers enhanced performance and higher reliability, and reduces overall cost. Each tap can drive up to ten 74LS loads. The MXD1005 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin MAX package, as well as an 8-pin SO or DIP, allowing full compatibility with the DS1005 and other delay line products.
____________________________Features
o Improved Second Source to DS1005 o Available in Space-Saving 8-Pin MAX Package o 17mA Supply Current vs. Dallas' 40mA o Low Cost o Delay Tolerance of 2ns or 3%, whichever is Greater o TTL/CMOS-Compatible Logic o Leading- and Trailing-Edge Accuracy o Custom Delays Available
MXD1005
________________________Applications
Clock Synchronization Digital Systems
______________Ordering Information
PART MXD1005C/D__ MXD1005PA__ MXD1005PD__ MXD1005SA__ MXD1005SE__ MXD1005UA__ TEMP. RANGE 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE Dice* 8 Plastic DIP 14 Plastic DIP 8 SO 16 Narrow SO 8 MAX
_________________Pin Configurations
TOP VIEW
IN 1 TAP2 2 8 7 VCC TAP1 TAP3 TAP5
*Dice are tested at TA = +25C. Note: To complete the ordering information, fill in the blank with the part number extension from the Part Number and Delay Times table to indicate the desired delay per output.
MXD1005
TAP4 3 6 5 GND 4
_____Part Number and Delay Times
PART NUMBER EXTENSION (MXD1005_ _ __) DELAY (tPHL, tPLH) PER OUTPUT (ns) TAP4 TAP1 12 15 20 25 30 35 40 50 TAP2 24 30 40 50 60 70 80 100 TAP3 36 45 60 75 90 105 120 150 TAP4 48 60 80 100 120 140 160 200 TAP5 60 75 100 125 150 175 200 250
DIP/SO/MAX
IN 1 N.C. N.C. 2 3
14 VCC 13 N.C. 12 TAP1
60 75 100 125 150 175 200 250
TAP2 4 N.C. 5 TAP4 6 GND 7
MXD1005
11 N.C. 10 TAP3 9 8 N.C. TAP5
DIP
Note: Contact factory for characterization data. Functional Diagram appears at end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
5-Tap Silicon Delay Line MXD1005
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.5V to +6V All Other Pins..............................................-0.5V to (VCC + 0.5V) Short-Circuit Output Current (1sec) ....................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.1mW/C above +70C) ......727mW 14-Pin Plastic DIP (derate 10.0mW/C above +70C) ..800mW 8-Pin SO (derate 5.9mW/C above +70C)..................471mW 16-Pin Narrow SO (derate 8.7mW/C above +70C) ....696mW 8-Pin MAX (derate 4.1mW/C above +70C) .............330mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V 5%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Supply Voltage Input Voltage High Input Voltage Low Input Leakage Current Active Current Output Current High Output Current Low Input Capacitance SYMBOL VCC VIH VIL IL ICC IOH IOL CIN (Note 2) (Note 2) (Note 2) 0V VIN VCC VCC = 5.25V, period = minimum (Notes 3, 4) VCC = 4.75V, VOH = 4.0V VCC = 4.75V, VOL = 0.5V TA = +25C (Note 5) 12 5 10 -1 17 CONDITIONS MIN 4.75 2.2 0.8 1 70 -1 TYP 5.00 MAX 5.25 UNITS V V V A mA mA mA pF
TIMING CHARACTERISTICS
(VCC = +5.0V 5%, TA = +25C, unless otherwise noted.) PARAMETER Input Pulse Width Input-to-Tap Delay (leading edge) Input-to-Tap Delay (trailing edge) Power-Up Time Period Note 1: Note 2: Note 3: Note 4: SYMBOL tWI tPLH tPHL tPU (Note 6) 4(tWI) CONDITIONS (Note 6) (Notes 7-10) (Notes 7-10) MIN 40% of TAP5 tPLH See Part Number and Delay Times table See Part Number and Delay Times table 100 TYP MAX UNITS ns ns ns ms ns
Note 5: Note 6: Note 7: Note 8: Note 9: Note 10:
Specifications to -40C are guaranteed by design, not production tested. All voltages referenced to GND. Measured with outputs open. ICC is a function of frequency and TAP5 delay. Only an MXD1005_ _60 operating with a 40ns period and VCC = +5.25V will have a maximum ICC of 70mA. For example, an MXD1005_ _100 will not exceed 30mA. See Supply Current vs. Input Frequency graph in Typical Operating Characteristics. Guaranteed by design. Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.). VCC = +5V at +25C. Typical delays are accurate on both rising and falling edges within 2ns or 3%. See Test Conditions section. The combination of temperature variations from +25C to 0C or +25C to +70C and voltage variation from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional typical input-to-tap delay shift of 1.5ns or 4%, whichever is greater. All taps and outputs delays tend to vary unilaterally with temperature or supply variations. For example, if TAP1 slows down, all other taps will also slow down; TAP3 cannot be faster than TAP2.
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_______________________________________________________________________________________
5-Tap Silicon Delay Line
__________________________________________Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
MXD1005
ACTIVE CURRENT vs. FREQUENCY
50% DUTY CYCLE 17 ACTIVE CURRENT (mA) 16 15 14 13 12 11 MXD1005_ _200 10 0.001 0.01 0.1 FREQUENCY (MHz) 1 10 MXD1005_ _75
MXD1005 TOC4
MXD1005_ _75 PERCENT CHANGE IN DELAY vs. TEMPERATURE
1.5 % CHANGE IN DELAY (TAP2) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) RELATIVE TO NOMINAL (+25C) tPHL tPLH tPLH tPHL
MXD1005 TOC1
18
2.0
MXD1005_ _100 TO MXD1005_ _200 PERCENT CHANGE IN DELAY vs. TEMPERATURE
MXD1005 TOC2
MXD1005_ _250 PERCENT CHANGE IN DELAY vs. TEMPERATURE
1.5 % CHANGE IN DELAY (TAP2) 1.0 0.5 0 -0.5 tPLH -1.0 -1.5 -2.0 RELATIVE TO NOMINAL (+25C) -40 -20 0 20 40 60 80 100 tPHL tPHL tPLH
MXD1005 TOC3
2.0 1.5 % CHANGE IN DELAY (TAP2) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 20 40 60 80 RELATIVE TO NOMINAL (+25C) tPHL tPLH tPLH tPHL
2.0
100
TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
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5-Tap Silicon Delay Line MXD1005
______________________________________________________________Pin Description
PIN 8-PIN DIP/SO/MAX 1 2 3 4 5 6 7 8 -- 14-PIN DIP 1 4 6 7 8 10 12 14 2, 3, 5, 9, 11, 13 16-PIN SO 1 4 6 8 9 11 13 16 2, 3, 5, 7, 10, 12, 14, 15 NAME IN TAP2 TAP4 GND TAP5 TAP3 TAP1 VCC N.C. Signal Input 40% of specified maximum delay 80% of specified maximum delay Device Ground 100% of maximum specified delay 60% of specified maximum delay 20% of specified maximum delay Power-Supply Input No Connection. Not internally connected. FUNCTION
Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________Definitions of Terms
Period: The time elapsed between the first pulse's leading edge and the following pulse's leading edge. Pulse Width (t WI): The time elapsed on the pulse between the 1.5V level on the leading edge and the 1.5V level on the trailing edge, or vice-versa. Input Rise Time (tRISE): The time elapsed between the 20% and 80% points on the input pulse's leading edge. Input Fall Time (tFALL): The time elapsed between the 80% and 20% points on the input pulse's trailing edge. Time Delay, Rising (tPLH): The time elapsed between the 1.5V level on the input pulse's leading edge and the corresponding output pulse's leading edge. Time Delay, Falling (tPHL): The time elapsed between the 1.5V level on the input pulse's trailing edge and the corresponding output pulse's trailing edge.
____________________Test Conditions
Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Times: Pulse Width: +25C 3C +5V 0.01V High = 3.0V 0.1V Low = 0.0V 0.1V 50 max 3.0ns max 500ns max
Period: 1s Each output is loaded with a 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edges. The time delay due to the 74F04 is subtracted from the measured delay.
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_______________________________________________________________________________________
5-Tap Silicon Delay Line MXD1005
VCC
(+5V)
PERIOD
0.1F TIME MEASUREMENT UNIT
tRISE VIH IN VIL 2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
1.5V
IN 50 20% TAP1
tWI
20%
TAP2
tPHL
MXD1005
20% TAP3
tPLH
20% TAP4
1.5V OUT
1.5V
20%
TAP5
74FO4
Figure 1. Timing Diagram
Figure 2. Test Circuit
__________Applications Information
Supply and Temperature Effects on Delay
Variations in supply voltage may affect the MXD1005's fixed tap delays. Supply voltages beyond the specified range may result with larger variations. The devices are internally compensated to reduce the effects of temperature variations. Although these devices might vary with supply and temperature, the delays vary unilaterally, which suggests that TAP3 can never be faster than TAP2.
Capacitance and Loading Effects on Delay
The output load can affect the tap delays. Larger capacitances tend to lengthen the rising and falling edges, thus increasing the tap delays. As the taps are loaded with other logic devices, the increased load will increase the tap delays.
Board Layout Considerations/Decoupling
The device should be driven with a source that can deliver the required current for proper operation. A 0.1F ceramic bypassing capacitor could be used. The board should be designed to reduce stray capacitance.
_______________________________________________________________________________________
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5-Tap Silicon Delay Line MXD1005
_________________________________________________________Functional Diagram
TAP1
TAP2
TAP3
TAP4
TAP5
IN
20%
20%
20%
20%
20%
MXD1005
____Pin Configurations (continued)
TOP VIEW
___________________Chip Information
TRANSISTOR COUNT: 824
IN 1 N.C. 2 N.C. 3 TAP2 4 N.C. 5 TAP4 6 N.C. 7 GND 8
16 VCC 15 N.C. 14 N.C.
MXD1005
13 TAP1 12 N.C. 11 TAP3 10 N.C. 9 TAP5
SO
6
_______________________________________________________________________________________
5-Tap Silicon Delay Line
________________________________________________________Package Information
8LUMAXD.EPS
MXD1005
_______________________________________________________________________________________
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5-Tap Silicon Delay Line MXD1005
___________________________________________Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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